Many modern high-speed memories, including, but not limited to, caches, register files, port buffer memories, content addressable memories (CAMs), etc., demand single-port and multi-port static random access memories (SRAMs) with fast access times. There are several known circuits and architectural techniques for speeding up a read data path in the memory/register file with a capability to speed up data flow through logic circuitry in the memory/register file. Read access time is often determined as a sum of the time to assert an enable signal on a selected word line (tWL), the time to discharge a corresponding bit line (tBL—DIS), the time to sense a bit line signal developed on the bit line (tSEN), and the time to transfer data indicative of the sensed bit line signal to a read output port of the memory (tTRANS). Read access time is a critical timing parameter that limits the cycle time of the memories.